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STA510
60V 5A POWER FULL BRIDGE
PRODUCT PREVIEW
s
MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION 150m RdsON NDMOS OUTPUT STAGE CMOS COMPATIBLE LOGIC INPUTS THERMAL PROTECTION WARNING OUTPUT: THERMAL, OVERLOAD UNDER VOLTAGE PROTECTION ON VREG OVERVOLTAGE PROTECTION TWO LEVELS CURRENT PROTECTION
MULTIPOWER BCD TECHNOLOGY
s s s s s s s
Flexiwatt27 ORDERING NUMBER: STA510
DESCRIPTION STA510 is a monolithic full bridge stage in Multipower BCD Technology. The device is particularly designed to make the output stage of classD audio amplifier capable to deliver 100W undistorted output power on 8 load. The input pins have threshold proportional to VIbias pin voltage. The commutation speed of the output stage is settable with an extenal resistor (Curref pin) to choice for each application the best compromise of THD versus EMI and current AUDIO APPLICATION CIRCUIT
spikes. The overcurrent protection works in two steps, the first one, at a lower value limits the current terminating the pulse (independently to the input) when the current in the power output MOS reaches a first threshold: it is aimed to act in case of overload and its effect is to stabilize the mean current in the load to a limit value. The second step shuts down completely the device and restarts the power on sequence if the current reaches a second (higher) threshold: it is aimed to act in case of short circuit, when the first limitation can fail.
SUB_GND
1,27
9 7 Q1 + DRIVER L Q3 PROTECTIONS & LOGIC 10 11 14 12 13 19 21 Q2 17 DRIVER R REGULATOR Q4 18
BOOTL VCCL
C3 100nF VCC
INL +3.3V VIBIAS PWRDIN FAULT R2 10K C1 100nF WARNING INR VSS
4 26 3 5
C15 100nF OUTL OUTL SUB PWGNDL PWGNDL BOOTR VCCR C16 100nF OUTR OUTR
C12 1F L1 22H
C11 1000F
R1 10K
TRISTATE
6
R4 20 C5 330pF R5 6
C6 100nF C7 100nF C10 470nF 8
2 24 25
C4 100nF
C13 1F
R6 6
C8 100nF C9 100nF
VREGBOOT VCC_REG VREG C2 470nF R3 48K
24 23 20
L2 22H
CURREF
22
15 16
PWGNDR PWGNDR
D03AU1508
July 2003
This is preliminary information on a new product now in development. Details are subject to change without notice.
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STA510
PIN FUNCTION
N 1, 27 2 3 4 5 6 7 8 9 10, 11 12,13 14 15, 16 17, 18 19 20 21 22 23 24 25 26 Pin SUB_GND WARNING PWRDN INL FAULT TRISTATE VCCL VREG_BOOT BOOTL OUTL PWRGNDL SUB PWRGNDR OUTR BOOTR VREG VCCR CURREF VCC_REG INR VSS VIBIAS Substrate (frame) and signal ground Warning advisor St-by input pin Input left arm Fault adviosor Hi-Z input pin Positive power supply left arm VREG input for bootstrap charging Bootstrap cap. left arm Output left arm Power GND left arm Substrate (plug near powers) Power GND right arm Output right arm Bootstrap cap. right arm Regulator output (for filtering) Positive power supply right arm Resistor for commutation speed setting Positive power supply for the regulator Input right arm Input logic ground High logic state setting voltage Description
FUNCTIONAL PIN STATUS
PIN NAME FAULT FAULT* TRI-STATE TRI-STATE PWRDN PWRDN WARNING WARNING* Logical value 0 1 0 1 0 1 0 1 IC -STATUS Fault detected (Short circuit, or Thermal ..) Normal Operation All powers in Hi-Z state Normal operation Low absorpion Normal operation Temperature of the IC =130C; overload Normal operation
* : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor.
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STA510
PIN CONNECTION
1
27
SUB_GND
TRISTATE
INL
BOOTL
OUTL
OUTL
OUTR
OUTR
BOOTR
FAULT
SUB
WARNING
PWRGNDL
PWRGNDL
PWRGNDR
PWRGNDR
CURREF
PWRDN
VCCL
VREG
VCCR
VREG_BOOT
VCC_REG
INR
VSS
VIBIAS
D03AU1455
ABSOLUTE MAXIMUM RATINGS
Symbol VCE Vmax VREG vod Top Tstg, Tj Parameter DC Supply Voltage (VCCR, VCCL, VCC_REG) Logic Voltage (INL, INR, VIBIAS, TRISTATE, PWRDN) Regulator Voltage (VREG, VREG_BOOT, CURREF) Voltage on Open Drain Pins (WARNING, FAULT) Operating Temperature Range Storage and Junction Temperature Value 60 5.5* 8 60 0 to 70 -40 to 150 Unit V V V V C C
*: referred to VSS
ELECTRICAL CHARACTERISTCS (VIbias = 3.3V; Vcc = 45V; Tamb = 25C unless otherwise specified referred to "AUDIO APPLICATION CIRCUIT" pag. 1)
Symbol RdsON Idss GNH GNL Dt-s Dt-d td ON td OFF Parameter Power Nchannel MOSFET RdsON Id=1A; Power Nchannel leakage Idss Power Nchannel RdsON Matching Id = 1A; High Right with High Left Power Nchannel RdsON Matching Id = 1A; Low Right with Low Left Low current Dead Time (static) see test circuit in fig. 1 95 95 20 40 40 80 100 100 Test conditions Min. Typ. 0.15 TBD Max. 0.20 Unit A % % ns ns ns ns
High current Dead Time (dinamic) Id = 5A; see fig 3 Turn-on delay time Turn-off delay time Resistive load Resistive load;
SUB_GND
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STA510
ELECTRICAL CHARACTERISTCS (continued)
Symbol tr tf VCC VIN-H VIN-L IIN-H IIN-L Rise time Fall time Supply voltage operating range High level input voltage Low level input voltage Hi level Input current Low level input current Pin voltage = VIbias Pin voltage = 0.3V Ibias = 3.3V Ibias = 3.3V Ibias = 3.3V PWRDN = 0; TRISTATE = 0 PWRDN = 1; Tri-state=0; No LOAD Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 6 7 0.8 35 1 1.9 0.25 TBD 100 2.2 Parameter Test conditions Resistive load; Resistive load; 11 Min. Typ. Max. 50 50 55 V Ibias/2 VIbias/2 +150mV +300mV VIbias/2 VIbias/2 -300mV -130mV 1 1 Unit ns ns V V V A A A V V mA mA mA
IPWRDN-H Hi level PWRDN pin input current VL VH IVCCPWRDN IVCC-hiz IVCC Low logical state voltage (pin PWRDN, TRISTATE) High logical state voltage (pin PWRDN, TRISTATE) Supply current from Vcc in Power Down Supply current from Vcc in Tristate Supply current from Vcc in operation
Ilim Isc VUV VOV VDROP
Current Limit (Overload) Short circuit current threshold Undervoltage protection threshold on VREG Overvoltage protection threshold on VCC Dropout from VCC to VREG
7 8 7
8 9
A A V V V
55
60 4
LOGIC TRUTH TABLE (see fig. 2)
TRI-STATE 0 1 1 1 1 INL x 0 0 1 1 INR x 0 1 0 1 HSL (Q1) OFF OFF OFF ON ON HSR (Q2) OFF OFF ON OFF ON LSL (Q3) OFF ON ON OFF OFF LSR (Q4) OFF ON OFF ON OFF OUTPUT MODE Hi-Z DUMP NEGATIVE POSITIVE Not used
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STA510
Figure 1. Test Circuit.
OUTx Vcc (3/4)Vcc Dt_s = Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50% OUTx DTr DTf
INx
R 8
+ -
vdc = Vcc/2
gnd
D03AU1507
Figure 2.
+VCC
Q1 INL OUTL
Q2 OUTR INR
Q3
Q4
GND
D03AU1456
Figure 3.
Dt_d = High Current Dead time for Bridge application = ABS(DTout(L)-DTin(L))+ABS(DTOUT(R)-DTin(R)) +VCC Duty cycle=A Duty cycle=B
DTout(L) Q1 Q2 Rload=8 22H 22H DTout(R) OUTR
DTin(A) INL
OUTL Iout=5A Q3
DTin(R) INR
Iout=5A Q4
470nF
470nF
470nF
Duty cycle A and B: Fixed to have DC output current of 5A in the direction shown in figure
D03AU1457
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STA510
mm TYP. 4.50 1.90 1.40 0.90 0.39 1.00 26.00 29.23 17.00 12.80 0.80 22.47 18.97 15.70 7.85 5 3.5 4.00 4.00 2.20 2 1.70 0.5 0.3 1.25 0.50 inch TYP. 0.177 0.074 0.055 0.035 0.015 0.040 1.023 1.150 0.669 0.503 0.031 0.884 0.747 0.618 0.309 0.197 0.138 0.157 0.157 0.086 0.079 0.067 0.02 0.12 0.049 0.019
DIM. A B C D E F (1) G G1 H (2) H1 H2 H3 L (2) L1 L2 (2) L3 L4 L5 M M1 N O R R1 R2 R3 R4 V V1 V2 V3
MIN. 4.45 1.80 0.75 0.37 0.80 25.75 28.90
MAX. 4.65 2.00 1.05 0.42 0.57 1.20 26.25 29.30
MIN. 0.175 0.070 0.029 0.014 0.031 1.014 1.139
MAX. 0.183 0.079 0.041 0.016 0.022 0.047 1.033 1.153
OUTLINE AND MECHANICAL DATA
22.07 18.57 15.50 7.70
22.87 19.37 15.90 7.95
0.869 0.731 0.610 0.303
0.904 0.762 0.626 0.313
3.70 3.60
4.30 4.40
0.145 0.142
0.169 0.173
5 (Typ.) 3 (Typ.) 20 (Typ.) 45 (Typ.)
Flexiwatt27 (vertical)
(1): dam-bar protusion not included (2): molding protusion included
V C B V H H1 H3 H2 R3 R4 V1 R2 R L L1 A
V3
L4
O
L2
N
L3
V1
V2
R2 L5 G G1 F
R1 R1 R1 E
FLEX27ME
D
Pin 1
M
M1
7139011
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STA510
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (R) 2003 STMicroelectronics - All Rights Reserved DDX is a trademark of Apogee tecnology inc. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
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